Operation and Timing of Sequential Logic Circuits
Summary
This activity uses Simulink to help students explore the operation and timing of sequential logic circuits. Students begin by constructing and simulating an SR latch, then progressively use their working circuits to build a D latch, D flip-flop, 2-bit register, and a larger sequential logic circuit.
Throughout the activity, students use timing diagrams and simulation results to compare observed circuit behavior with expected theoretical behavior. They vary input and clock periods, investigate simulation errors and unexpected outputs, and determine the conditions under which their circuits operate as expected. The activity emphasizes troubleshooting and interpretation rather than simply constructing working circuits, requiring students to explain discrepancies between ideal sequential logic behavior and their simulation results.
CollapseLearning Goals
Construct and simulate increasingly complex sequential logic circuits, including SR latches, D latches, D flip-flops, and registers.
Use timing diagrams to analyze the relationship between inputs, clock or enable signals, and outputs.
Investigate how changes in signal periodicity affect circuit operation.
Compare simulated circuit behavior with expected behavior based on sequential logic theory and truth tables.
Identify and troubleshoot simulation errors and unexpected circuit behavior.
Explain timing differences between input and output signals and determine conditions under which a simulated circuit operates as expected.